The present invention relates generally to the field of substrate processing equipment. More particularly, the present invention relates to methods and system for providing temperature control of a semiconductor substrate disposed between a bake plate and an opposing face plate.
Modern integrated circuits contain millions of individual elements that are formed by patterning the materials, such as silicon, metal and/or dielectric layers, that make up the integrated circuit to sizes that are small fractions of a micrometer. The technique used throughout the industry for forming such patterns is photolithography. A typical photolithography process sequence generally includes depositing one or more uniform photoresist (resist) layers on the surface of a substrate, drying and curing the deposited layers, patterning the substrate by exposing the photoresist layer to electromagnetic radiation that is suitable for modifying the exposed layer and then developing the patterned photoresist layer.
It is common in the semiconductor industry for many of the steps associated with the photolithography process to be performed in a multi-chamber processing system (e.g., a cluster tool) that has the capability to sequentially process semiconductor wafers in a controlled manner. One example of a cluster tool that is used to deposit (i.e., coat) and develop a photoresist material is commonly referred to as a track lithography tool.
Track lithography tools typically include a mainframe that houses multiple chambers (which are sometimes referred to herein as stations) dedicated to performing the various tasks associated with pre- and post-lithography processing. A typically dry processing chamber within a track lithography tool include a thermal control unit that house a bake and/or chill plate on which a wafer substrate can be loaded opposing a face plate. The loaded wafer substrate usually is supported on a plurality of proximity pins forming a thermal conductive air gap with a predetermined separation. Track lithography tools also frequently include one or more pod/cassette mounting devices, such as an industry standard FOUP (front opening unified pod), to receive wafer substrates from and return wafer substrates to the clean room, multiple transfer robots to transfer wafer substrates between the various chambers/stations of the track tool and an interface that allows the tool to be operatively coupled to a lithography exposure tool in order to transfer wafer substrates into the exposure tool and receive wafer substrates from the exposure tool after the wafer substrates are processed within the exposure tool.
Over the years there has been a strong push within the semiconductor industry to shrink the size of semiconductor devices. The reduced feature sizes have caused the industry's tolerance to process variability to shrink, which in turn, has resulted in semiconductor manufacturing specifications having more stringent requirements for process uniformity and repeatability. An important factor in minimizing process variability during track lithography processing sequences is to ensure that every wafer substrate processed within the track lithography tool for a particular application has the same “wafer history.” A substrate's wafer history is generally monitored and controlled by process engineers to ensure that all of the device fabrication processing variables that may later affect a device's performance are controlled, so that all substrates in the same batch are always processed the same way.
To ensure that each substrate has the same “wafer history” requires that each wafer substrate experiences the same repeatable substrate processing steps (e.g., consistent coating process, consistent hard bake process, consistent chill process, and the like) and the timing between the various processing steps is the same for each substrate. Lithography type device fabrication processes can be especially sensitive to variations in process recipe variables and the timing between the recipe steps, which directly affects process variability and ultimately device performance. Thus, there is a need in the art for improved methods and systems for providing improved bake processes for semiconductor substrates on a bake plate opposing a face plate.